University of Bahrain
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FPGA-Based MWD for Network Error Correction

Show simple item record El-Medany,Wael M. 2018-07-31T08:47:52Z 2018-07-31T08:47:52Z 2015
dc.identifier.issn 2210-1519
dc.description.abstract This paper presents reconfigurable hardware architecture for MWD (Minimum Weight Decoding) algorithm for network error correction, with high throughput on Field Programmable Gate Array (FPGA). Network Error Correction (NEC) is used for detecting and correcting the errors in noisy communication channels when multicasting a source message to a set of nodes. Minimum Weight Decoding (MWD) algorithm is a cyclic linear block codes that are used as Forward Error Correcting (FEC) codes. The design can be reconfigured for different message length and different generator number, the encoder and decoder has been described using VHDL (VHSIC Hardware Description Language). The decoder has the ability to detect and correct different types and different numbers of errors based on the message length and the length of redundant data. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level. en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-ShareAlike 4.0 International *
dc.rights.uri *
dc.subject FPGA
dc.subject MWD
dc.subject VHDL
dc.subject Embedded Networks
dc.title FPGA-Based MWD for Network Error Correction en_US
dc.type Article en_US
dc.volume 03
dc.issue 02
dc.source.title International Journal of Computing and Network Technology
dc.abbreviatedsourcetitle IJCNT

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