Compact and High Speed Point Multiplication Architecture for Elliptic Curve Diffie-Hellman Algorithm on Reconfigurable Computing

Abstract

Elliptic curve cryptography is popular for its efficiency and strong security as it provides equivalent security strength using smaller key sizes compared to other public key algorithms such as RSA that commonly use larger key sizes for the same level of security. Point multiplication is the core of elliptic curve cryptography. The development of reconfigurable devices enables researchers to exploit effective methods for implementation of efficient hardware based scalar multiplication. Modern FPGAs consist embedded hard-cores useful for design flexibility in addition to traditional generic fabrics. For cryptosystems implementation, several researchers used traditional logic elements, and only some have used embedded hard-cores including DSP slices and block RAMs. However complex cryptographic algorithms require large amount of generic logic and that in turn effect performance. Utilizing hard-cores entirely excludes flexibility of logic elements. Balanced utilization of these resources is considered in this research. Thus, for elliptic curve scalar multiplication required for implementing Elliptic Curve Diffie-Hellman algorithm, the FPGAs' hard-cores are used; while, simpler arithmetic and logical operations are flexibly implemented utilizing the generic FPGA fabrics. With this approach, a new architecture is proposed and implemented based on Montgomery algorithm with projective coordinates for point multiplication. Cascaded DSP48E1 slices are used with parallel-pipeline approach together with block RAMs for effective implementation. Compared to existing research outcomes reported in the literature, for implementation of the proposed architecture on Kintex-7 platform, smaller hardware resources (971 slices, 4BRAMs, and 32 DSP slices) are utilized with timing performance of 1.74 µs. Whereas, 1164 slices, 4 BRAMs, and 32 DSP slices are used with enhanced timing performance of 1.55 µs for implementation of the architecture on Virtex-7 platform