Performance Evaluation of Highly Efficient XOR and XOR-XNOR Topologies using CNTFET for Nanocomputation

Abstract

With excessive scaling in the VLSI industry, the Carbon Nanotube Field Effect Transistor(CNTFET) is emerging as a potential replacement to traditional MOSFET technology. XOR gate is an essential component in various digital logic circuit designs. Therefore it is crucial to devise a high performing XOR gate and XOR-XNOR gate to increase the overall efficiency of various XOR based digital circuits. This paper investigates the performance of several designs of individual XOR gates as well as simultaneous XOR-XNOR circuits for different applications. The implemented circuits have been analyzed and compared by parameters namely transistor count, delay, power dissipation, and power-delay product, and Energy delay product. The driving capability of the circuits has been verified for load capacitance of 2fF to 100fF. All circuits are simulated using Cadence Virtuoso Analog Environment in 45nm MOS technology and 10nm CNTFET model at 0.6-1.4V supply. The noise margin analysis of each XOR gate is also carried out. The most efficient topologies for individual XOR and XOR-XNOR circuits are found to be ~97% more efficient than their counterparts. The layouts of the most efficient topologies have been implemented to calculate the circuit area. Monte Carlo simulation is done to establish the circuit’s reliability. The implemented circuits perform remarkably better with a 10nm CNTFET model, thereby establishing emerging CNTFET technology as a promising replacement to MOSFET.