A Complete Verification of a Full Search Motion Estimation Engine

Abstract

A Full Search Motion Estimation architecture design is proposed and fully elaborated and tested in this paper. The proposed Motion Estimation architecture smartly reuses the data fetched from the main memory to be used in the search area. This allows using less memory I/O bandwidth. The proposed architecture guarantees a full utilization of all resources and not to have any stall at all during the Motion Estimation process. The proposed architecture guarantees high speed by performing the Motion Estimation process in adequate number of clock cycles. Additionally, high video quality is obtained using the proposed architecture. Both of the high speed and the high video quality are achieved by using an efficient algorithm to load the search area into a local memory. The local memory efficiently loads the processing array with the required search area and achieving two data reuse levels. We concentrate on elaborating and functionally testing the whole Motion Estimation architecture using VHDL verification language and provide a proof for the high accuracy of the designed architecture. The design of the local memory is implemented using only registers and a simple counter. This simplifies the design by avoiding the use of complicated addressing to write or read into/from the local memory. The proposed architecture has a regular data flow which leads to a simple VLSI implementation. The proposed architecture is flexible and can be used for low and high definition video sequences. Due to the high speed of the proposed architecture, it can be used for many real time video applications such as video phones, video conference, and HDTV broad casting.