dc.contributor.author | Phu Phu, Tran Nguyen | |
dc.contributor.author | Gia Han, Dang Phuong | |
dc.contributor.author | Cong Luong, Nguyen | |
dc.contributor.author | Van Cuong, Nguyen | |
dc.date.accessioned | 2020-07-21T11:38:47Z | |
dc.date.available | 2020-07-21T11:38:47Z | |
dc.date.issued | 2021-01-01 | |
dc.identifier.issn | 2210-142X | |
dc.identifier.uri | https://journal.uob.edu.bh:443/handle/123456789/4004 | |
dc.description.abstract | Static Random-Access Memory (SRAM) has become phenomenally crucial to a board spectrum of VLSI designs and applications, ranging from high-performance CPUs to low-power mobile hand-held devices. As technology scaling helps to drive density and performance, it also poses some technical challenges in designing. This paper presents the pre-layout design for a 32kbit 6T synchronous single-port SRAM using 4-bit column multiplexer method and 28nm technology. Several sessions of this paper list out some methods such as self-control the timing constraints of the design, optimize shape and size to reduce difference in delay paths, thus improve performance. | en_US |
dc.language.iso | en | en_US |
dc.publisher | University of Bahrain | en_US |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 International | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject | SRAM, VLSI, 32kbit, 6T, single-port, synchronous, column multiplexer | en_US |
dc.title | DESIGN A SYNCHRONOUS SINGLE-PORT SRAM 1024x32xMUX4 USING 28NM TECHNOLOGY | en_US |
dc.type | Article | en_US |
dc.identifier.doi | http://dx.doi.org/10.12785/ijcds/100110 | |
dc.volume | 10 | en_US |
dc.issue | 1 | |
dc.pagestart | 103 | en_US |
dc.pageend | 109 | en_US |
dc.source.title | International Journal of Computing and Digital Systems | en_US |
dc.abbreviatedsourcetitle | IJCDS | en_US |
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