University of Bahrain
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Novel Ultra Low Power-Delay-Product Full Adder Cells in 45nm Fin-FET Technology

Show simple item record Golmakani*,Samira Rostami* Golmakani*,Abbas 2018-07-31T08:45:43Z 2018-07-31T08:45:43Z 2014
dc.identifier.issn 2210-1519
dc.description.abstract A full adder is one of the most commonly used circuit component, many improvements have been made to refine the architecture of a full adder. The general goal of our work is to reduce power-delay-product (PDP). In this paper two novel 13- transistor CMOS 1-bit Full Adder cell is proposed. The first proposed full adder is based on two stage XOR gate with combined GDI technology and transmission gate. The second proposed full adder uses the low power designs of the XOR and XNOR gates and MUX (2-TR). Our new full adders have been contrasted with following full adders: Conventional CMOS full adder, Complementary Pass Logic, transmission gate adder and transmission function adder. The power and speed has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 45nm Fin-FET predictive model. en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-ShareAlike 4.0 International *
dc.rights.uri *
dc.subject Full Adder cell
dc.subject GDI technology
dc.subject Transmission gate
dc.subject XOR gate
dc.subject sub-threshold voltage FinFET (sub-FinFET)
dc.title Novel Ultra Low Power-Delay-Product Full Adder Cells in 45nm Fin-FET Technology en_US
dc.type Article en_US
dc.volume 02
dc.issue 02
dc.source.title International Journal of Computing and Network Technology
dc.abbreviatedsourcetitle IJCNT

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