Novel Ultra Low Power-Delay-Product Full Adder Cells in 45nm Fin-FET Technology

Abstract

A full adder is one of the most commonly used circuit component, many improvements have been made to refine the architecture of a full adder. The general goal of our work is to reduce power-delay-product (PDP). In this paper two novel 13- transistor CMOS 1-bit Full Adder cell is proposed. The first proposed full adder is based on two stage XOR gate with combined GDI technology and transmission gate. The second proposed full adder uses the low power designs of the XOR and XNOR gates and MUX (2-TR). Our new full adders have been contrasted with following full adders: Conventional CMOS full adder, Complementary Pass Logic, transmission gate adder and transmission function adder. The power and speed has been carried out using extensive simulation on HSPICE circuit simulator. The simulation results are based on 45nm Fin-FET predictive model.