University of Bahrain
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Design of Two High Performance 1-Bit CMOS Full Adder Cells

Show simple item record Naghizadeh, Hamid Reza Moghadam, Mohammad Sarvghad Tous, Saber Izadpanah Golmakani, Abbas 2018-07-05T10:19:07Z 2018-07-05T10:19:07Z 2013
dc.identifier.issn 2210-142X
dc.description.abstract 1-bit full adder is a very great part in the design of application particular integrated circuits. Power consumption is one of the most significant parameters of full adders. Therefore reducing power consumption in full adders is very important in low power circuits. In this paper, we propose two new structures of hybrid full adders. The first full adder implemented by combining the Swing Restored Lass-transistor Logic and Branch-Based Logic that called, SRPL-BBL cell and the second full adder implemented by combining the Gate-Diffusion Input technique and Majority function that called, GDI-Majority cell. All of the capacitors in this paper replaced with MOSCAP. Simulation results performed by HSPICE in TSMC 0.13 μm CMOS process. The results indicate the superiority the proposed full adders against several low power 1-bit full adder cells in terms of delay, power consumption, and power delay product (PDP). en_US
dc.language.iso en_US en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-ShareAlike 4.0 International *
dc.rights.uri *
dc.subject 1-bit full adder en_US
dc.subject Low power en_US
dc.subject SRPL en_US
dc.subject BBL en_US
dc.subject GDI en_US
dc.title Design of Two High Performance 1-Bit CMOS Full Adder Cells en_US
dc.type Article en_US
dc.volume 02
dc.issue 01
dc.source.title International Journal of Computing and Digital Systems
dc.abbreviatedsourcetitle IJCDS

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