University of Bahrain
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Analysis on Digital Implementation of Sigma-Delta ADC with Passive Analog Components

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dc.contributor.author Palagiri, HarshaVardhini
dc.contributor.author Makkena, MadhaviLatha
dc.contributor.author Chantigar, KrishnaReddy
dc.date.accessioned 2018-07-05T10:28:57Z
dc.date.available 2018-07-05T10:28:57Z
dc.date.issued 2013
dc.identifier.issn 2210-142X
dc.identifier.uri http://10.7.0.19:8080/xmlui/handle/123456789/223
dc.description.abstract Sigma-Delta Analog to Digital Converter with digital implementation techniques is simulated. The differential pin based and inverter based architectures are discussed. Simulation of the proposed architecture with Virtex-4 FPGA I/Os is performed and analysis carried out using HSPICE to estimate the typical achievable clock speeds. The results demonstrate 200MHz clock speeds on LVPECL differential input pin for comparator action. Subsequently MATLAB simulation is carried out to simulate the digital blocks of SD-ADC. The results show promising direction of research for realizing SD-ADCs with only passive analog components outside the FPGA/ASIC. en_US
dc.language.iso en_US en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-ShareAlike 4.0 International *
dc.rights.uri http://creativecommons.org/licenses/by-nc-sa/4.0/ *
dc.subject sigma-delta ADC en_US
dc.subject differential I/Os en_US
dc.subject all-digital-ADC en_US
dc.subject spartan-6 IBISmodel simulation en_US
dc.subject Select-IO technology, SFDR en_US
dc.title Analysis on Digital Implementation of Sigma-Delta ADC with Passive Analog Components en_US
dc.type Article en_US
dc.identifier.doi http://dx.doi.org/10.12785/IJCDS/020203
dc.volume 02
dc.issue 02
dc.source.title International Journal of Computing and Digital Systems
dc.abbreviatedsourcetitle IJCDS


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