University of Bahrain
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A Low Power Parallel Sequential Decoder for Convolutional Codes

Show simple item record EL Bourichi, Adil 2018-07-05T10:39:23Z 2018-07-05T10:39:23Z 2013
dc.identifier.issn 2210-142X
dc.description.abstract A novel decoding algorithm having a simple hardware realization is proposed for convolutional codes. The proposed decoder accepts a simple implementation in hardware in terms of area occupancy and power consumption compared to other decoders for convolutional codes such as those based on the Viterbi algorithm (VA). Furthermore, the processing delays due to looking back and forward in a trellis as in sequential decoding algorithms are avoided, which makes the proposed decoder suitable for fast high data rates wireless communication systems. Simulation results show a comparable bit error rate (BER) performance to optimal decoders with a reduction of power consumption of 60% compared to Viterbi decoders en_US
dc.language.iso en_US en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-ShareAlike 4.0 International *
dc.rights.uri *
dc.subject Convolutional codes en_US
dc.subject low power decoders en_US
dc.subject sequential decoding en_US
dc.subject wireless communication en_US
dc.title A Low Power Parallel Sequential Decoder for Convolutional Codes en_US
dc.type Article en_US
dc.volume 02
dc.issue 02
dc.source.title International Journal of Computing and Digital Systems
dc.abbreviatedsourcetitle IJCDS

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