Evaluation of Artificial Neural Network Architectures for Pattern Recognition on FPGA

Abstract

In this paper, we present the design and implementation of two hardware architectures, namely MHL-ANN and SHL-ANN, for the realization of artificial neural networks on reconfigurable computing platforms like FPGA. We use 16-bit half-precision floating-point number format to represent the weights of the designed networks. The networks are synthesized and verified on Xilinx Virtex-5 XC5VLX-110T FPGA. We study the scalability and hardware resource utilization of the two proposed neural network architectures. For performance evaluation, the handwritten digit recognition application with MNIST database is performed, which reported a recognition rate of 90.88% when using an MHL-ANN architecture of size 20-12-10 and a recognition rate of 96.83% when using an SHL-ANN architecture of size 784-40-10. Experimental results showed that the SHL-ANN architecture is very potential for high performance embedded recognition applications.