FPGA Implementation of Enhanced JPEG Algorithm for Colored Images

Abstract

Image quality and size have been growing very fast over the last decades requiring large storage space and high transmission rate. Image compression is an efficient method used to reduce the size of the image. JPEG algorithm has been considered as one of the famous techniques used for image compression. This paper proposed and implemented an optimized hardware solution called Hybrid Compression using Faster Color Conversion and Run Length (HC-FCC-RL) algorithm for JPEG algorithm based on FPGA to reduce the latency and accelerate the compression process. The paper also proposed a Fast Color Conversion with Approximation (FCCA) step to accelerate the conversion process from RGB to YCbCr. Using approximate techniques will reduce the number of resources used as well as the latency with some percentage error. In addition, the paper proposed a Parallel Run Length (P-RL) algorithm to speed up the design. The enhancement approach in this paper aimed to optimize the overall design of the JPEG algorithm targeting color images. To evaluate the performance of the proposed framework, the HC-FCC-RL architecture was implemented in Verilog and synthesized on FPGA board. The color conversion architecture uses 331 logic elements, a latency of 13.930 ns for converting the three colors component of blocks and a power dissipation of 861.03 mW. The percentage errors for the color conversion is 11.6%, 1.8% and 5.3% for Y, Cb, Cr components, respectively. The Run Length algorithm performs better than existing work by saving 48.36% in logic elements, 53.79% in latency and 62.86% in power dissipation. Thus, the proposed work demonstrated superior performance compared to current work in the literature.