Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications

Abstract

This paper presents different power efficient multiply accumulate architectures based on modified parallel prefix adders. A general multiply accumulate unit consists of a multiplier, an adder and an accumulator. The multiplier used in this study is a Vedic multiplier and the parallel prefix adders that are brought into this research include Kogge Stone adder, Brent Kung adder, Han Carlson adder and Hybrid Han Carlson adder. The pre-processing and post-processing stages in those adders which mainly consists of exclusive OR operations are modified using a switch level model of the exclusive OR gate. The corresponding modified adder is also used in the Vedic multiplier for adding the partial products. The performance analysis of the different multiply accumulate models is done in terms of power and figure of merit. The proposed modified multiply accumulate units showed significant improvement in power consumption and figure of merit. The various architectures are designed using verilog hardware description language. The models are simulated and synthesized using Xilinx Vivado Design Suite 2015.2 for Artix-7 field programmable gate array family with xc7a100tcsg324-1 as the target device with -1 speed grade.