University of Bahrain
Scientific Journals

FPGA-based Acceleration for Convolutional Neural Networks on PYNQ-Z2

Show simple item record Viet Huynh, Thang 2021-08-13T16:58:46Z 2021-08-13T16:58:46Z 2021-08-13
dc.identifier.issn 2210-142X
dc.description.abstract Convolutional neural network is now widely used in computer vision and deep learning applications. The most compute-intensive layer in convolutional neural networks is the convolutional layer, which should be accelerated in hardware. This paper aims to develop an efficient hardware-software co-design framework for machine learning applications on the PYNQ-Z2 board. To achieve this goal, we develop hardware implementations of convolutional IP core and use them as Python overlays. Experiments show that the hardware implementations of the convolutional IP core outperform their software implementations by factors of up to 9 times. Furthermore, we make use of the designed convolutional IP core as hardware accelerator in the handwritten digit recognition application with MNIST dataset. Thanks to the use of the hardware accelerator for the convolutional layers, the execution performance of the convolutional neural network has been improved by a factor of 6.2 times en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-NoDerivatives 4.0 International *
dc.rights.uri *
dc.subject FPGA en_US
dc.subject Convolutional Neural Netwok en_US
dc.subject Hardware Accelerator en_US
dc.subject Python en_US
dc.subject PYNQ en_US
dc.title FPGA-based Acceleration for Convolutional Neural Networks on PYNQ-Z2 en_US
dc.contributor.authorcountry Danang City, Vietnam en_US
dc.contributor.authoraffiliation Faculty of Electronics and Telecommunication Engineering, The University of Danang - University of Science and Technology en_US
dc.source.title International Journal Of Computing and Digital System en_US
dc.abbreviatedsourcetitle IJCDS en_US

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