Performance and Area Optimization of SRAM Cell in Nanocomputing Application

Abstract

A Shrink in technology leads to decrease in voltage supply which returns in power leakage. This affects the data stability in Static Ram Access Memory (SRAM) cell. Static noise margin (SNM) is need for measurement of data stability in SRAM cell. Data stability for SRAM cell relies on largest DC noise which can be ignored at the inverters outputs which are cross coupled without change the data in SRAM cell. This paper presents 6T, 7T, 8T, 9T, 10T design and analysis which increases the data stability of SRAM during write and read mode. These cells are compared with respect to their read static noise margin (RSNM), hold noise margin (HSNM), write 0 delay, write 1 delay, average write delay, static power, average dynamic power, total power dissipation and surface area. Finger method is used to create layout of different SRAM cell which reduces the surface area of cell. This method also required to reduces the parasitic in layout design. The layout of different cell of SRAM and an SRAM with 4×4 array of 6T cell is implemented on virtuoso tool of cadence software using 45nm Technology. After the simulation outcome it has found that that 10T cell has maximum RSNM which is 0.42V and it has minimum total power dissipation. 10T SRAM cell has average dynamic power 154.309nW, static power 1.14022μW and total power dissipation 1.294529μW. Process variation and Monte Carlo simulation for different SRAM cells are carried out. Process variation is done for the RSNM parameter of the memory cells. Monte Carlo simulation is carried out for average dynamic power, static power, rise time and fall time using 2000 samples. After the simulation it is observed that the performance of 10T design is best among all simulated SRAM cells. Comparison of 6T, 8T and 9T cell design with previous work shows the improvement in RSNM at the price of write delay. 10T SRAM cell using CNFET (carbon nanotube field-effect transistor) is simulated which has channel length of 11nm at 0.3V of voltage supply. After simulation it has observed that 10T SRAM cell based on CNFET has low total power of dissipation.