Abstract:
High speed multipliers are the primary requirement of multi-core processors because of key applications like high performance and security requires well designed and reliable hardware implementations. The overall performance of a particular processor is based on the speed of the multiplier unit inside it. This paper presents implementation of low power FIR Filter using karatsuba multiplier. Multiplier is designed using gates. Implementation of FIR Filter using karatsuba multiplier and array multiplier is done .The simulation of various parameters such as delay, area and power are carried out and these parameters are reduced in FIR filter using karatsuba multiplier. Estimated power of filter using array multiplier and karatsuba multiplier is 5.7μW and 3.13 μW respectively. 45% of power and 37% of area can be reduced by using this implementation
