University of Bahrain
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Low Power FIR Filter using Karatsuba Multiplier

Show simple item record Wilson, Shiny P. P., Ramesh 2018-07-31T08:42:36Z 2018-07-31T08:42:36Z 2016
dc.identifier.issn 2210-1519
dc.description.abstract High speed multipliers are the primary requirement of multi-core processors because of key applications like high performance and security requires well designed and reliable hardware implementations. The overall performance of a particular processor is based on the speed of the multiplier unit inside it. This paper presents implementation of low power FIR Filter using karatsuba multiplier. Multiplier is designed using gates. Implementation of FIR Filter using karatsuba multiplier and array multiplier is done .The simulation of various parameters such as delay, area and power are carried out and these parameters are reduced in FIR filter using karatsuba multiplier. Estimated power of filter using array multiplier and karatsuba multiplier is 5.7μW and 3.13 μW respectively. 45% of power and 37% of area can be reduced by using this implementation en_US
dc.language.iso en en_US
dc.publisher University of Bahrain en_US
dc.rights Attribution-NonCommercial-ShareAlike 4.0 International *
dc.rights.uri *
dc.subject Array Multiplication
dc.subject Karatsuba Algorithm
dc.subject FIR filter
dc.subject Verilog
dc.subject CADENCE
dc.title Low Power FIR Filter using Karatsuba Multiplier en_US
dc.type Article en_US
dc.volume 04
dc.issue 01
dc.source.title International Journal of Computing and Network Technology
dc.abbreviatedsourcetitle IJCNT

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