Abstract:
Reducing power consumption and improving performance are crucial requirements for many applications, especially power hungry and time-consuming applications. This is particularly true when these applications are running in power or time-constrained environments like battery-operated embedded systems or on Internet of Things (IoT) devices. A general-purpose processor is not promising for this kind of application as it cannot provide optimized performance and power consumption for specific applications. That is why domain-specific architectures (DSA) are gaining popularity, as they promise optimized performance for these types of applications in terms of throughput, power consumption, and overall cost. Unfortunately, the use of DSA presents inherent limitations as it requires custom design for each group of applications and cannot offer optimized performance for each specific application. This paper explains how to take advantage of the open standard Instruction Set Architecture (ISA) of the fifth generation of Reduced Instruction Set Computers (RISC-V) to automate the generation of a uni-processor core customized for a certain application such that the processor supports only the very specific instructions needed by this application. The proposed generator is capable of producing the Register Transfer Level (RTL) description of a processor core for any desired application given its source code. This work targets Field Programmable Gate Arrays (FPGAs) due to their reconfigurability. When compared with general-purpose processors, the conducted experiments show that application-specific cores generated by our approach managed to achieve energy and execution time reductions reaching 8% and 5% respectively on some of the used benchmarks. The proposed methodology also offers the added flexibility stemming from the possibility to automatically re-configure the FPGA when a new or upgraded software application that would benefit from modifying the set of supported instructions is deployed.
