dc.contributor.author |
Yehia, Omar |
|
dc.contributor.author |
Raafat, Sandra |
|
dc.contributor.author |
El-kharashi, Watheq |
|
dc.contributor.author |
Wahba, Ayman |
|
dc.contributor.author |
Salama, Cherif |
|
dc.date.accessioned |
2024-07-24T21:17:10Z |
|
dc.date.available |
2024-07-24T21:17:10Z |
|
dc.date.issued |
2024-07-24 |
|
dc.identifier.uri |
https://journal.uob.edu.bh:443/handle/123456789/5834 |
|
dc.description.abstract |
Reducing power consumption and improving performance are crucial requirements for many applications, especially power
hungry and time-consuming applications. This is particularly true when these applications are running in power or time-constrained
environments like battery-operated embedded systems or on Internet of Things (IoT) devices. A general-purpose processor is not
promising for this kind of applications as it cannot provide optimized performance and power consumption for specific applications.
That is why domain-specific architectures (DSA) are gaining popularity, as they promise optimized performance for these types of
applications in terms of throughput, power consumption, and overall cost. Unfortunately, the use of DSA presents inherent limitations
as it requires custom design for each group of applications and cannot offer optimized performance for each specific application.
This paper explains how to take advantage of the open standard Instruction Set Architecture (ISA) of the fifth generation of Reduced
Instruction Set Computer (RISC-V) to automate the generation of a uni-processor core customized for a certain application such that the
processor supports only the very specific instructions needed by this application. The proposed generator is capable of producing the
Register Transfer Level (RTL) description of a processor core for any desired application given its source code. This work targets Field
Programmable Gate Arrays (FPGAs) due to their re-configurability. When compared with general purpose processors, the conducted
experiments show that application specific cores generated by our approach managed to achieve energy and execution time reductions
reaching 8% and 5% respectively on some of the used benchmarks. The proposed methodology also offers the added flexibility
stemming from the possibility to automatically re-configure the FPGA when a new or upgraded software application that would benefit
from modifying the set of supported instructions is deployed. |
en_US |
dc.language.iso |
en_US |
en_US |
dc.publisher |
University of Bahrain |
en_US |
dc.subject |
Power Consumption |
en_US |
dc.subject |
Performance |
en_US |
dc.subject |
Embedded Systems |
en_US |
dc.subject |
Instruction-Level Customization |
en_US |
dc.subject |
RISC-V |
en_US |
dc.subject |
Rocket Chip |
en_US |
dc.subject |
FPGA |
en_US |
dc.subject |
Core-generation |
en_US |
dc.title |
Instruction-Level Customization and Automatic Generation of Embedded Systems Cores for FPGA |
en_US |
dc.identifier.doi |
XXXXXX |
|
dc.volume |
17 |
en_US |
dc.issue |
1 |
en_US |
dc.pagestart |
1 |
en_US |
dc.pageend |
11 |
en_US |
dc.contributor.authorcountry |
Cairo, Egypt |
en_US |
dc.contributor.authoraffiliation |
Computer and Systems Engineering Department,Ain Shams University |
en_US |
dc.contributor.authoraffiliation |
Computer Science and Engineering Department, The American University in Cairo |
en_US |
dc.source.title |
International Journal of Computing and Digital Systems |
en_US |
dc.abbreviatedsourcetitle |
IJCDS |
en_US |